Comp Arch - Lecture 6

Performing the operation.

Ensuring that the system operates correctly and reliably over its intended lifespan.

Adjusting the voltage and frequency of the processor based on workload to reduce power consumption.

Using architectural features to enhance security.

Registers, cache, main memory, and secondary storage.

Data is written only to the cache, and main memory is updated later.

Occur when a program writes data beyond the allocated buffer.

Field-Programmable Gate Arrays.

Any memory location can be stored in any location in the cache.

Includes all other hardware components in a computing system, such as memory controllers, I/O devices, etc.

Storing the result of the operation.

Each memory location maps to a specific location in the cache.

Buffer overflows, Spectre, and Meltdown.

Managing and dissipating heat generated by the processor and other components.

Dynamic Voltage and Frequency Scaling (DVFS).

The overlapping of the execution of multiple instructions to improve throughput.

The implementation of the ISA, including the organization of the CPU, cache, and memory system.

Data is written to both the cache and main memory simultaneously.

Design choices that impact a system's security.

Minimizing power consumption to reduce heat and extend battery life.

Reduced Instruction Set Computing.

Designing processors to perform well on specific types of workloads.

Write-through and write-back.

Executing multiple threads simultaneously on different cores or processors.

Application-Specific Integrated Circuits.

Executing instructions in a different order than they appear in the program to avoid stalls.

Fetching, decoding, executing, and storing.

Temporal Locality and Spatial Locality

Defines what operations the CPU can perform.

Executing multiple instructions in the same clock cycle.

Small, fast memory used to store frequently accessed data.

Long-term storage for data and programs (e.g., hard drives, SSDs).

Accelerators, FPGAs, and ASICs.

Redundancy, error correction codes, and fault tolerance.

Specialized processors designed for parallel processing, particularly for graphics and compute-intensive tasks.

Randomizing the memory locations of key data areas to make it harder for attackers to exploit vulnerabilities.

Vulnerabilities that allow attackers to access sensitive data by exploiting speculative execution.

A processor with multiple cores on a single chip, allowing multiple threads to execute simultaneously.

Address space layout randomization (ASLR) and hardware-based security features.

Heat sinks, fans, and liquid cooling.

Superscalar execution and out-of-order execution.

Small, fast storage locations in the CPU used to hold data and instructions being actively used.

The primary memory used to store programs and data that are currently being used by the CPU.

Adding extra components or data to detect and correct errors.

Overlapping the execution of multiple instructions to improve throughput.

Determining what operation needs to be performed.

Using cache memory to reduce the average access time to memory.

Application-Specific Integrated Circuits; integrated circuits designed for a specific application.

Address Space Layout Randomization.

Complex Instruction Set Computing; has a large set of complex instructions.

Retrieving the instruction from memory.

MIPS, ARM, x86

If a piece of data is accessed, it is likely to be accessed again in the near future.

Field-Programmable Gate Arrays; integrated circuits that can be configured after manufacturing.

It states that the speedup of a program using multiple processors is limited by the fraction of the program that can be parallelized.

Pipelining, parallelism, and caching.

Multicore processors and GPUs.

Specialized hardware units designed to accelerate specific tasks.

Features built into the hardware to protect against certain types of attacks.

Amdahl's Law

Techniques used to improve the performance of a computer system.

Dynamic Voltage and Frequency Scaling.

The interface between hardware and software, defining instructions, data types, addressing modes, etc.

Executing multiple threads simultaneously on different cores or processors.

Direct-mapped, fully associative, and set-associative.

Computer architecture deals with the engineering considerations involved in designing a computer.

A compromise between direct-mapped and fully associative, where the cache is divided into sets, and each memory location maps to a specific set.

Executing multiple instructions from a single thread simultaneously.

If a piece of data is accessed, data nearby in memory is likely to be accessed soon.

Executing multiple instructions from a single thread simultaneously.

Energy efficiency, thermal management, and reliability.

Complex Instruction Set Computing.

Designing systems that can continue to operate correctly even in the presence of faults.

The ability to perform multiple operations simultaneously using multiple execution units or cores.

The interface between hardware and software, defining instructions, data types, addressing modes, etc.

Instruction Set Architecture (ISA), Microarchitecture, and System Design.

Reduced Instruction Set Computing; has a smaller set of simpler instructions.

Codes used to detect and correct errors in memory and storage systems.

Performing multiple operations simultaneously using multiple execution units or cores.

Instruction-level parallelism (ILP) and thread-level parallelism (TLP).

Jump to effective address given by operand

Stack grows towards smaller addresses; stack size is static and predetermined.

Overflow Flag

je (jump if equal), jg (jump if greater), jl (jump if less), etc.

Used to compare two 8, 16, or 32-bit numbers by performing subtraction without saving the result.

Uses the CX register as a loop counter and decrements it, looping if CX ≠ 0.

Flags are set according to the result of the subtraction operation.

Get the flags register from the stack.

Makes the program execution jump to a specific label or address if the condition is true.

PUSH (push operand onto stack), POP (pop operand from stack)

Full 3 hours, in person, written by hand without outside notes, worth 24% of final grade, covers lectures 1-5.

push ax; push dx; call myproc; ...

Zero Flag

Direction Flag

PUSH all general-purpose registers onto the stack.

Defined after they are called, before end of code segment

The OS steps in and kills program.

MASM generates code for 8086 by default. use .186, .286, .386 directive in the first line of your code to solve.

Procedures should not push to stack without popping

LIFO (Last In, First Out)

Parity Flag

SP holds an effective address, while SS holds a physical address.

Performs a bitwise AND operation like the AND instruction, but does not modify the source and destination.

Store the flags register in the stack.

Trace (Trap) Flag

SHL (Shift Logical Left), SHR (Shift Logical Right)

ROL (Rotate Left), ROR (Rotate Right)

Sign Flag

Interrupt Enable Flag

AND, OR, XOR, NOT

Get all general-purpose registers from the stack.

Auxiliary Carry Flag

Pop return address from stack and Jump to that address

Makes the program execution jump to a specific label or address unconditionally.

Callee-saved: procedure clears out some registers for its own use. Caller-saved: calling program saves the registers that it does not want the procedure to overwrite.

CLC (Clear Carry Flag), STC (Set Carry Flag), CLD (Clear Direction Flag), STD (Set Direction Flag), CLI (Clear Interrupt Flag), STI (Set Interrupt Flag), CMC (Complement Carry Flag), LAHF (Load AH from flags)

Carry Flag

Segment addresses are shifted 4 bits to the left before adding the offset.

The return address (IP) is pushed to the stack.

Use registers, or pass parameters on the stack.

SAL (Shift Arithmetic Left), SAR (Shift Arithmetic Right)

RCL (Rotate Left Through Carry), RCR (Rotate Right Through Carry)